1. Field of the Invention
The present invention relates to a memory access apparatus that can speed up memory access.
2. Description of the Related Art
Recently, digital control is utilized in various electronic products such as television and audio devices. With the advancement of technology, speedup is achieved for a clock signal that controls electronic circuits configuring these electronic products.
For this purpose, various technologies have been developed (see, e.g., Japanese Patent Application Laid-Open Publication No. 2002-64368).
An example of a memory system 1010 shown in FIG. 10 will be described.
A DSP 210 is a digital signal processing apparatus extensively used in DVD players, etc., to digitally process music data and image data and is an apparatus writing data into a memory 110 and reading data from the memory 110.
A “CLK” terminal is a terminal that loads a clock signal from the outside. The DSP 210 performs control for access to the memory 110 in synchronization with the rising edge of this clock signal. An “n_BDAA” terminal is a terminal that outputs address information indicating an address of data stored in the memory 110. An “XBDAWR” terminal is a terminal that outputs a command (write command) instructing data write to the memory 110. An “XBDARD” terminal is a terminal that outputs a command (read command) instructing data read from the memory 110. A “BDA_W” terminal is a terminal that outputs write data to the memory 110. A “BDA_R” terminal is a terminal that loads read data from the memory 110.
If a “CEN” terminal=L and a “WEN” terminal=L, the memory 110 writes the data input to a “D” terminal into an address identified by the address information at the timing of the rising edge of the clock signal input to a “/CLK” terminal. If the “CEN” terminal=L and the “WEN” terminal=H, the memory 110 outputs from a “Q” terminal the data stored at an address identified by the address information at the timing of the rising edge of the clock signal input to the “/CLK” terminal.
The memory access of the DSP 210 can be pipelined by disposing an address latch unit 500. FIGS. 11A and 11B depict how the memory access is pipelined. Since the memory access is pipelined, the DSP 210 can sequentially output the address information for each timing of rising edge of the clock signal without waiting for the completion of the data read/write process in the memory 110. This achieves fast memory access.
FIG. 12 shows a time chart when the DSP 210 reads data from the memory 110 in the memory system 1010 shown in FIG. 10.
FIG. 13 shows a time chart when data are written into the memory 110 in the memory system 1010 shown in FIG. 10.
The speedup of the memory access is achieved in the memory system 1010 by pipelining the memory access and by inputting to the memory 110 the clock signal inverted from the clock signal input to the DSP 210.
However, in the case of the data read, as shown in FIG. 12, only T1 is defined as a time interval after read data are output from the “Q” terminal of the memory 110 until the read data are loaded through the “BDA_R” terminal of the DSP 210. T1 is on the order of about ½ cycle of the clock signal. In the case of the data write, as shown in FIG. 13, only T3 is defined as a time interval after write data are output from the “BDA_W” terminal of the DSP 210 until the write data are loaded through the “D” terminal of the memory 110. T3 also is on the order of about ½ cycle of the clock signal.
This is the cause of preventing the speedup of the clock signal of the memory system 1010. That is, although values of T1 and T3 are reduced as the clock signal is speeded up, the clock signal can only be speeded up within a frequency range with T1>0 and T3>0. Therefore, the shortness of T1 and T3 becomes the cause of preventing the speedup of the clock signal and the speedup of the memory access.